Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

US7863136B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Matthias Goldbach · Dresden, DE
• Jessica Hartwich · Neubiberg, DE
• Lars Dreeskornfeld · Dresden, DE
• Arnd Scholz · Poughkeepsie, US
• Tobias Mono · Dresden, DE

Key dates

• Filing date: Sep 30, 2008
• Grant date: Jan 4, 2011
• Expiry date: Dec 3, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.