Method for integrating SiGe NPN and vertical PNP devices
US7863148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
Abstract
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.