Methods for full gate silicidation of metal gate structures
US7863192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.