Patent · US Active

Test circuit, wafer, measuring apparatus, and measuring method

US7863925B2 · kind B2 · utility

2Cited by

5References

18Claims

0Family size

Assignee

National University Corporation Tohoku University · JP

Inventors

Shigetoshi Sugawa · Atsugi, JP
Akinobu Teramoto · Sendai, JP

Key dates

Filing date	Sep 19, 2007
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Feb 24, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2884
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.