Flexible delay cell architecture
US7863931B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Dec 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.