Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same
US7863957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Feb 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.