Apparatus and methods for a high-voltage latch
US7863959B2 · kind B2 · utility
3Cited by
13References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Aug 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.