Three-dimensional chip-stack synchronization
US7863960B2 · kind B2 · utility
30Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.