Patent · US Active

Erase verify for memory devices

US7864583B2 · kind B2 · utility

1Cited by

57References

26Claims

0Family size

Assignee

Atmel Corporation · US

Inventors

Stefano Surico · Milano, IT
Marco Passerini · Lozza, IT
Fablo Tassan Caser · Arcore, IT
Simone Bartoll · Pessano, IT

Key dates

Filing date	Aug 19, 2008
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Sep 22, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/0483
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.