Patent · US Active

Data receiver with clock recovery circuit

US7864907B2 · kind B2 · utility

1Cited by

5References

24Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Martin Streibl · Petershausen, DE
Peter Gregorius · Munich, DE
Thomas Rickes · Munich, DE
Ralf-Rainer Schledz · St. Margarethen, AT

Key dates

Filing date	Apr 30, 2007
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Sep 26, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/007
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.