Configurable high-speed memory interface subsystem
US7865661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2008 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.