Patent · US Active

Controlling cleaning of data values within a hardware accelerator

US7865675B2 · kind B2 · utility

10Cited by

2References

27Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Nigel C. Paver · Austin, US
Stuart David Biles · Cambridge, GB

Key dates

Filing date	Dec 6, 2007
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Mar 20, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1027
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.