Patent · US Active

Method and apparatus for dynamic system-level frequency scaling

US7865749B2 · kind B2 · utility

4Cited by

6References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Peter A. Sandon · South Burlington, US
Cedric Lichtenau · Stuttgart, DE
Martin Recktenwald · Eppelheim, DE
Thomas Pflueger · Echterdingen, DE
Rolf Hilgendorf · Eppelheim, DE

Key dates

Filing date	Oct 31, 2003
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Aug 24, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/08
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.