Processor including efficient signature generation for logic error protection
US7865770B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2008 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Jan 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.