Patent · US Active

System and method for system-on-chip interconnect verification

US7865789B2 · kind B2 · utility

1Cited by

11References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Serafino Bueti · Waterbury, US
Adam J. Courchesne · Granby, US
Kenneth J. Goodnow · South Burlington, US
Gregory J. Mann · Colorado Springs, US
Jason M. Norman · South Burlington, US
Stanley B. Stanski · South Burlington, US
Scott T. Vento · Santa Clara, US

Key dates

Filing date	Jun 28, 2007
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Dec 3, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318513
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.