Patent · US Active

Method and system for generating a layout for an integrated electronic circuit

US7865855B2 · kind B2 · utility

8Cited by

5References

9Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Juergen Koehl · Holzgerlingen, DE
Matthias Ringe · Lörrach, DE

Key dates

Filing date	Nov 20, 2007
Grant date	Jan 4, 2011
Priority date	—
Expiry date	Mar 6, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source is disclosed. The source supplies a plurality of signals to the respective plurality of sinks. The method includes: identifying the source which supplies at least one of the respective sinks and having a negative slack; finding all sinks having a negative slack driven by the source; clustering the sinks according to timing and placement information read from a database, yielding a plurality of clusters of sinks, in which each cluster includes only a predetermined portion of the plurality of sinks; generating a plurality of clones associated with a respective one of the clusters of sinks; and coupling the clones to respective ones of the clusters of sinks yielding a second layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.