Patent · US Active

Method of forming an interconnect structure on an integrated circuit die

US7867889B2 · kind B2 · utility

13Cited by
5References
8Claims
0Family size

Assignee

Inventor

Key dates

Filing dateNov 24, 2005
Grant dateJan 11, 2011
Priority date—
Expiry dateJul 6, 2026

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76867
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.