MOS device with a high voltage isolation structure
US7868422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2005 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jul 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.