Semiconductor package having non-aligned active vias
US7868459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2006 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jun 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.