Receiver circuit for use in a semiconductor integrated circuit
US7868663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Dec 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.