Phase change memory erasable and programmable by a row decoder
US7869268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.