Circuit for locking a delay locked loop (DLL) and method therefor
US7869287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Feb 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.