Semiconductor memory device having advanced tag block
US7870362B2 · kind B2 · utility
12Cited by
20References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Jul 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.