Error detection device for an address decoder, and device for error detection for an address decoder
US7870473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2007 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Aug 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.