Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
US7870528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | Jan 11, 2011 |
| Priority date | — |
| Expiry date | Mar 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.