Extremely-thin silicon-on-insulator transistor with raised source/drain
US7871869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.