Method for forming metal gates in a gate last process
US7871915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.