Multi-layered metal line of semiconductor device for preventing diffusion between metal lines and method for forming the same
US7872351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.