Die stacking system and method
US7872356B2 · kind B2 · utility
7Cited by
4References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.