Memory controller calibration
US7872494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jul 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.