In package ESD protections of IC using a thin film polymer
US7872841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jul 14, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.