Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor
US7872937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.