Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip
US7873066B2 · kind B2 · utility
8Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Jan 26, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jul 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, system and computer program product for arbitrarily aligning vector operands, which are transmitted in inter-thread communication buffer packets within a highly threaded Network On a Chip (NOC) processor, are presented. A set of multiplexers in a node in the NOC realigns and extracts data word aggregations from an incoming compressed inter-thread communication buffer packet. The extracted data word aggregations are used as operands by an execution unit within the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.