Digital phase relationship lock loop
US7873762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2009 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Jul 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.