Processor utilizing a loop buffer to reduce power consumption
US7873820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Nov 15, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides processing systems, apparatuses, and methods that reduce power consumption with the use of a loop buffer. In an embodiment, an instruction fetch unit of a processor initially provides instructions from an instruction cache to an execution unit of the processor. While instructions are provided from the instruction cache to the execution unit, instructions forming a loop are stored in a loop buffer. When a loop stored in the loop buffer is being iterated, the instruction cache is disabled to reduce power consumption and instructions are provided to the execution unit from the loop buffer. When the loop is exited, the instruction cache is re-enabled and instructions are provided to the execution unit from the instruction cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.