Methods for practical worst test definition and debug during block based statistical static timing analysis
US7873926B2 · kind B2 · utility
7Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.