High-level language code sequence optimization for implementing programmable chip designs
US7873953B1 · kind B1 · utility
11Cited by
30References
24Claims
0Family size
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Key dates
| Filing date | Mar 20, 2006 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Nov 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.