Method of transistor level heterogeneous integration and system
US7875952B1 · kind B1 · utility
8Cited by
25References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jun 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherein alignment targets on the base semiconductor are used for precise lateral positioning of device structures above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.