Semiconductor device assembly having a stress-relieving buffer layer
US7875972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jun 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.