Semiconductor device
US7875986B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Mar 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.