Register data retention systems and methods during reprogramming of programmable logic devices
US7876125B1 · kind B1 · utility
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9Claims
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Key dates
| Filing date | May 12, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jun 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.