Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices
US7876137B2 · kind B2 · utility
3Cited by
1References
19Claims
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Key dates
| Filing date | Nov 20, 2008 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Nov 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.