Synchronization pulse generator with forced output
US7876141B2 · kind B2 · utility
0Cited by
3References
12Claims
0Family size
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Key dates
| Filing date | Oct 14, 2008 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Nov 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.