Content addressable memory having selectively interconnected rows of counter circuits
US7876590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Aug 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.