Single-event upset immune static random access memory cell circuit, system, and method
US7876602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.