Self-tuning of signal path delay in circuit employing multiple voltage domains
US7876631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2008 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jul 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.