Processor and interrupt handling method
US7877535B2 · kind B2 · utility
2Cited by
9References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 6, 2009 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Apr 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.