Patent · US Active

Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs

US7877649B2 · kind B2 · utility

7Cited by

7References

5Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Joerg Kliewer · Munich, DE
Manfred Proell · Dorfen, DE
Stephan Schroeder · Munich, DE
Georg Eggers · Birkenfeld, DE
Wolfgang Ruf · Friedberg, DE
Hermann Hass · Höhenkirchen-Siegertsbrunn, DE

Key dates

Filing date	Nov 2, 2007
Grant date	Jan 25, 2011
Priority date	—
Expiry date	Jun 30, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.