Accurately modeling an asynchronous interface using expanded logic elements
US7877717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jul 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.