Analog IC placement using symmetry-islands
US7877718B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | Jun 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each module not included in a symmetry group is represented by a separate node of the HB*-tree. Each symmetry group node maps to a symmetry island placement for the symmetry group satisfying all symmetry and other placement constraints on the symmetry group. The placement tool employs a simulated annealing technique to iteratively perturb the HB*-tree representation to produce a sequence of trial placements, and uses a cost function to evaluate the quality of each trial placement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.